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        <li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">template_project_syn (template_project_Implmnt)</b> 
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<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis -  </b> 
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<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a>  </li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#compilerReport3" target="srrFrame" title="">Compiler Constraint Applicator</a>  </li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#mapperReport5" target="srrFrame" title="">Pre-mapping Report</a>  
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<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#mapperReport6" target="srrFrame" title="">Clock Summary</a>  </li></ul></li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#mapperReport7" target="srrFrame" title="">Mapper Report</a>  
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<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#clockReport8" target="srrFrame" title="">Clock Conversion</a>  </li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#timingReport9" target="srrFrame" title="">Timing Report</a>  
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<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#performanceSummary10" target="srrFrame" title="">Performance Summary</a>  </li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#clockRelationships11" target="srrFrame" title="">Clock Relationships</a>  </li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#interfaceInfo12" target="srrFrame" title="">Interface Information</a>  </li></ul></li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\syntmp\template_project_srr.htm#resourceUsage13" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\template_project_Implmnt\template_project_cck.rpt" target="srrFrame" title="">Constraint Checker Report (13:55 15-Jul)</a>  </li></ul></li>
<li><a href="file:///K:\Drive\Projects\Lattice FPGA\Projects\template_project\template_project\stdout.log" target="srrFrame" title="">Session Log (13:55 15-Jul)</a>  
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